支持的芯片
IC |
RTL8721Dx |
RTL8720E |
RTL8726E |
RTL8730E |
|---|---|---|---|---|
支持状态 |
Y |
Y |
Y |
Y |
概述
真随机数生成器（TRNG）可生成全熵32位随机数据供应用程序使用。其核心组件包括动态熵源和内部调理模块。
该模块已通过NIST随机性测试，满足密码学应用的安全性要求。
特性
TRNG生成由熵源产生的32位真随机数
TRNG内部嵌入了一个健康测试单元和一个错误管理单元。
TRNG包含两个独立的FIFO：FIFO_NS和FIFO_S（更高优先级）
TRNG的吞吐量约为2Mbps
TRNG生成由熵源产生的32位真随机数
TRNG内部嵌入了一个健康测试单元和一个错误管理单元。
TRNG包含两个独立的FIFO：FIFO_NS和FIFO_S（更高优先级）
TRNG的吞吐量约为5Mbps
TRNG生成由熵源产生的32位真随机数
TRNG内部嵌入了一个健康测试单元和一个错误管理单元。
TRNG包含两个独立的FIFO：FIFO_NS和FIFO_S（更高优先级）
TRNG的吞吐量约为5Mbps
TRNG生成由熵源产生的32位真随机数
TRNG内部嵌入了一个健康测试单元和一个错误管理单元。
TRNG包含两个独立的FIFO：FIFO_NS和FIFO_S（更高优先级）
TRNG的吞吐量约为5Mbps
框图
TRNG的框图如下所示：
TRNG包含以下子模块：
Clock
TRNG bus clock is 40MHz.
Noise Source
The noise source is digital OSC, as a random number source, it is internally composed of ring oscillator.
TRNG control
A bit is added to control whether the control register can be accessed from non-secure world.
Ensure that the default setting for OSC can work. ROM will use it only without configuring ROSC.
This area is the real control register, and the Control_S is the access window in the secure world, Control_NS is the access window in the non-secure world.
Debias and LFSR and Extractor
A serial post-processing circuit
RCT and APT
Two health tests of NIST specification
Control_S
This area is the access window in the secure world; the real address is “Control”.
Status_S
Indicates the available data in FIFO_S.
Indicates whether an error has happened.
FIFO_S
FIFO size is 256 bits.
Only have one window register instead of all the registers.
Read and return all zero when FIFO is empty.
When the available data is less than 128 bits, hardware will fill the FIFO_S to full in a high priority.
Control_NS
This area is the access window in the non-secure world; the real address is “Control”.
Only can be accessed when S bit in Control is 0.
Status_NS
Indicates the available data in FIFO_NS
Indicates whether an error has happened.
FIFO_NS
FIFO size is 128 bits.
Only have one window register instead of all the registers.
Read and returns all zero when FIFO is empty.
This FIFO has a lower priority than FIFO_S. If available data is less than 128 bits in FIFO_S, hardware will not feed any data to this FIFO.
TRNG的框图如下所示：
TRNG包含以下子模块：
PLL
The PLL is a 300MHz~660MHz clock, and will be enabled by hardware.
Analog ROSC
The ROSC is a dedicated OSC, it can generate a random clock of 4MHz ~ 7MHz.
Take how to avoid power leakage into consideration when TRNG is power off.
Speed sensor
Use APB clock, 40MHz.
TRNG control
A bit is added to control whether the control register can be accessed from non-secure world.
Ensure that the default setting for OSC can work. ROM will use it only without configuring ROSC.
This area is the real control register, and the Control_S is the access window in the secure world, Control_NS is the access window in the non-secure world.
Health check and error detect
This block should work with the default setting.
Any error can trigger an interrupt, which will be used by software to reset the whole TRNG.
This block has an internal 1024 bits FIFO, which guarantees all the output has passed the APT test.
Control_S
This area is the access window in the secure world; the real address is “Control”.
Status_S
Indicates the available data in FIFO_S.
Indicates whether an error has happened.
FIFO_S
FIFO size is 256 bits.
Only have one window register instead of all the registers.
Read and return all zero when FIFO is empty.
When the available data is less than 128 bits, hardware will fill the FIFO_S to full in a high priority.
Control_NS
This area is the access window in the non-secure world; the real address is “Control”.
All the registers can be accessed only when
SECURITY_CONTROLfiled in Control Register is 0xA.
Status_NS
Indicates the available data in FIFO_NS
Indicates whether an error has happened.
FIFO_NS
FIFO size is 128 bits.
Only have one window register instead of all the registers.
Read and returns all zero when FIFO is empty.
This FIFO has a lower priority than FIFO_S. If available data is less than 128 bits in FIFO_S, hardware will not feed any data to this FIFO.
TRNG的框图如下所示：
TRNG包含以下子模块：
PLL
The PLL is a 300MHz~660MHz clock, and will be enabled by hardware.
Analog ROSC
The ROSC is a dedicated OSC, it can generate a random clock of 4MHz ~ 7MHz.
Take how to avoid power leakage into consideration when TRNG is power off.
Speed sensor
Use APB clock, 40MHz.
TRNG control
A bit is added to control whether the control register can be accessed from non-secure world.
Ensure that the default setting for OSC can work. ROM will use it only without configuring ROSC.
This area is the real control register, and the Control_S is the access window in the secure world, Control_NS is the access window in the non-secure world.
Health check and error detect
This block should work with the default setting.
Any error can trigger an interrupt, which will be used by software to reset the whole TRNG.
This block has an internal 1024 bits FIFO, which guarantees all the output has passed the APT test.
Control_S
This area is the access window in the secure world; the real address is “Control”.
Status_S
Indicates the available data in FIFO_S.
Indicates whether an error has happened.
FIFO_S
FIFO size is 256 bits.
Only have one window register instead of all the registers.
Read and return all zero when FIFO is empty.
When the available data is less than 128 bits, hardware will fill the FIFO_S to full in a high priority.
Control_NS
This area is the access window in the non-secure world; the real address is “Control”.
All the registers can be accessed only when
SECURITY_CONTROLfiled in Control Register is 0xA.
Status_NS
Indicates the available data in FIFO_NS
Indicates whether an error has happened.
FIFO_NS
FIFO size is 128 bits.
Only have one window register instead of all the registers.
Read and returns all zero when FIFO is empty.
This FIFO has a lower priority than FIFO_S. If available data is less than 128 bits in FIFO_S, hardware will not feed any data to this FIFO.
TRNG的框图如下所示：
TRNG包含以下子模块：
PLL
The PLL is a 300MHz~660MHz clock, and will be enabled by hardware.
Analog ROSC
The ROSC is a dedicated OSC, it can generate a random clock of 4MHz ~ 7MHz.
Take how to avoid power leakage into consideration when TRNG is power off.
Speed sensor
Use APB clock, 40MHz.
TRNG control
A bit is added to control whether the control register can be accessed from non-secure world.
Ensure that the default setting for OSC can work. ROM will use it only without configuring ROSC.
This area is the real control register, and the Control_S is the access window in the secure world, Control_NS is the access window in the non-secure world.
Health check and error detect
This block should work with the default setting.
Any error can trigger an interrupt, which will be used by software to reset the whole TRNG.
This block has an internal 1024 bits FIFO, which guarantees all the output has passed the APT test.
Control_S
This area is the access window in the secure world; the real address is “Control”.
Status_S
Indicates the available data in FIFO_S.
Indicates whether an error has happened.
FIFO_S
FIFO size is 256 bits.
Only have one window register instead of all the registers.
Read and return all zero when FIFO is empty.
When the available data is less than 128 bits, hardware will fill the FIFO_S to full in a high priority.
Control_NS
This area is the access window in the non-secure world; the real address is “Control”.
All the registers can be accessed only when
SECURITY_CONTROLfiled in Control Register is 0xA.
Status_NS
Indicates the available data in FIFO_NS
Indicates whether an error has happened.
FIFO_NS
FIFO size is 128 bits.
Only have one window register instead of all the registers.
Read and returns all zero when FIFO is empty.
This FIFO has a lower priority than FIFO_S. If available data is less than 128 bits in FIFO_S, hardware will not feed any data to this FIFO.
使用说明
若系统需启用安全属性，建议将TRNG设置为安全模式，确保其控制寄存器仅允许安全域（Secure World）访问，防止非安全域（Non-Secure World）非法操作。
当安全域与非安全域同时请求大量随机数据时：
来自安全域的请求会优先得到响应（更高优先级）。
安全域请求处理完毕后，才会响应来自非安全域的请求。
推荐调用
_rand()函数获取32位随机数，。