Features
On-chip boot ROM
Contains the bootloader with In-System Programming (ISP) facility
Secure boot process using the Ed25519 Cryptographic Algorithm
Suspend resume process for low power
Boot from NOR flash
PSRAM as a memory
On-chip boot ROM
Contains the bootloader with In-System Programming (ISP) facility
Secure boot process with multiple cryptographic algorithms of hardware or software engine
Suspend resume process for low power
Boot from NOR flash
PSRAM as a memory
On-chip boot ROM
Contains the bootloader with In-System Programming (ISP) facility
Secure boot process with multiple cryptographic algorithms of hardware or software engine
Suspend resume process for low power
Boot from NOR flash
PSRAM as a memory
On-chip boot ROM
Contains the bootloader with In-System Programming (ISP) facility
Secure boot process with multiple cryptographic algorithms of hardware or software engine
Suspend resume process for low power
Boot from NAND or NOR Flash
PSRAM or DDR as memory
Boot Address
On reset, the processor loads the PC with the value of the reset vector defined in the vector table, which is fixed by hardware. Both KM4 and KM0 boot from address 0x0000_0000
.
CPU |
Boot address |
Type |
---|---|---|
KM4 |
0x0000_0000 |
KM4 ITCM ROM |
KM0 |
0x0000_0000 |
KM0 ITCM ROM |
On reset, the processor loads the PC with the value of the reset vector defined in the vector table, which is fixed by hardware. Both KM4 and KR4 boot from the address 0x0000_0000
.
CPU |
Boot address |
Type |
---|---|---|
KM4 |
0x0000_0000 |
KM4 ITCM ROM |
KR4 |
0x0000_0000 |
KR4 ITCM ROM |
On reset, the processor loads the PC with the value of the reset vector defined in the vector table. For KM4 and KR4, this value is hardware-fixed at address 0. In contrast, the DSP uses a configurable value, starting from a user-defined address.
CPU |
Boot address |
Type |
---|---|---|
KM4 |
0x0000_0000 |
KM4 ITCM ROM |
KR4 |
0x0000_0000 |
KR4 ITCM ROM |
DSP |
User Configurable |
Flash/SRAM/PSRAM |
On reset, the processor loads the PC with the value of the reset vector defined in the vector table, which is fixed by hardware. KM0 (LP), KM4 (NP), and CA32 (AP) all boot from address 0x0000_0000
.
CPU |
Boot address |
Type |
---|---|---|
KM0 |
0x0000_0000 |
KM0 ITCM ROM |
KM4 |
0x0000_0000 |
KM4 ITCM ROM |
CA32 |
0x0000_0000 |
CA32 BUS ROM |
Pin Description
The SoC supports ISP (In-System Programming) via LOGUART (PB4
/ PB5
) or USB to download code into Flash. The ISP mode is determined by the state of PB5
when boot.
Boot Mode |
PB5 (DOWNLOAD_MODE) |
Description |
---|---|---|
No ISP |
HIGH |
ISP bypassed. The IC attempts to boot from Flash. |
ISP |
LOW |
The IC enters ISP via LOGUART or USB. |
The SoC supports ISP (In-System Programming) via LOGUART (PA19
/ PA20
) to download code into Flash. The ISP mode is determined by the state of PA20
when boot.
Boot Mode |
PA20 (DOWNLOAD_MODE) |
Description |
---|---|---|
No ISP |
HIGH |
ISP bypassed. The IC attempts to boot from Flash. |
ISP |
LOW |
The IC enters ISP via LOGUART. |
The SoC supports ISP (In-System Programming) via LOGUART (PA19
/ PA20
) to download code into Flash. The ISP mode is determined by the state of PA20
when boot.
Boot Mode |
PA20 (DOWNLOAD_MODE) |
Description |
---|---|---|
No ISP |
HIGH |
ISP bypassed. The IC attempts to boot from Flash. |
ISP |
LOW |
The IC enters ISP via LOGUART. |
The SoC supports ISP (In-System Programming) via LOGUART (PB23
/ PB24
) or USB to download code into Flash. The ISP mode is determined by the state of PB24
when boot.
Boot Mode |
PB24 (DOWNLOAD_MODE) |
Description |
---|---|---|
No ISP |
HIGH |
ISP bypassed. The IC attempts to boot from Flash. |
ISP |
LOW |
The IC enters ISP via LOGUART or USB. |
Note
After mass production, a specific eFuse bit can be programmed to permanently disable ISP mode.
Boot Flow
After power-up or hardware reset, the hardware will boot the KM4 core at 150MHz. The boot process is handled by the on-chip Boot ROM and is always executed by the KM4 core.
After executing the KM4 bootloader code, the KM4 will initialize the environment for the KM0 core.
KM4 boots ROM
KM4 ROM checks whether to enter ISP mode
KM4 secure boot, ROM verifies bootloader signature (optional)
KM4 boots to bootloader
KM4 bootloader set the frequency of SoC according to
ameba_bootcfg.c
KM4 bootloader establishes the non-secure execution environment according to
ameba_boot_trustzonecfg.c
if TrustZone is enabledKM4 bootloader assists KM0 images loading and signature verification (optional)
SoC boot flow
After power-up or hardware reset, the hardware will boot the KM4 core at 150MHz. The boot process is handled by the on-chip Boot ROM and is always executed by the KM4 core.
After executing the KM4 bootloader code, the KM4 will initialize the environment for the KR4 core.
KM4 boots ROM
KM4 ROM checks whether to enter ISP mode
KM4 secure boot, ROM verifies bootloader signature (optional)
KM4 boots to bootloader
KM4 bootloader set the frequency of SoC according to
ameba_bootcfg.c
KM4 bootloader establishes the non-secure execution environment according to
ameba_boot_trustzonecfg.c
if TrustZone is enabledKM4 bootloader assists KR4 images loading and signature verification (optional)
SoC boot flow
After power-up or hardware reset, the hardware will boot the KM4 core at 150MHz. The boot process is handled by the on-chip Boot ROM and is always executed by the KM4 core.
After executing the KM4 bootloader code, the KM4 will initialize the environment for the KR4 and DSP core.
KM4 boots ROM
KM4 ROM checks whether to enter ISP mode
KM4 secure boot, ROM verifies bootloader signature (optional)
KM4 boots to bootloader
KM4 bootloader set the frequency of SoC according to
ameba_bootcfg.c
KM4 bootloader establishes the non-secure execution environment according to
ameba_boot_trustzonecfg.c
if TrustZone is enabledKM4 bootloader assists KR4 images loading and signature verification (optional)
KM4 bootloader assists DSP images loading and signature verification (optional)
SoC boot flow
After power-up or hardware reset, the hardware will boot the KM4 core at 200MHz. The boot process is handled by the on-chip Boot ROM and is always executed by the KM4 core.
After executing the KM4 bootloader code, the KM4 will initialize the environment for the KM0 and CA32 core.
KM4 boots ROM
KM4 ROM checks whether to enter ISP mode
KM4 secure boot, ROM verifies bootloader signature (optional)
KM4 boots to bootloader
KM4 bootloader set the frequency of SoC according to
ameba_bootcfg.c
KM4 bootloader establishes the non-secure execution environment according to
ameba_boot_trustzonecfg.c
if TrustZone is enabledKM4 bootloader assists KM0 images loading and signature verification (optional)
KM4 bootloader assists CA32 images loading and signature verification (optional)
SoC boot flow
Boot from NOR or NAND Flash depends on the settings in OTP. Additionally, PSRAM or DDR can be selected for storing code and data.
Boot API
The API BOOT_Reason()
is used to obtain the cause of chip boot, and the function prototype is:
u32 BOOT_Reason(void);
The return value of this API will be printed via LOGUART, and the default return value is 0
when the chip is initially powered-on. The return value of re-boot caused by other reasons can be found in the following table.
Users can find macro-definitions about return value in the file sysreg_aon.h
.
Items |
Description |
---|---|
Introduction |
Get boot reason |
Parameter |
None |
Return |
Boot reason. It can be any of the following values or combinations:
|
Items |
Description |
---|---|
Introduction |
Get boot reason |
Parameter |
None |
Return |
Boot reason. It can be any of the following values or combinations:
|
Items |
Description |
---|---|
Introduction |
Get boot reason |
Parameter |
None |
Return |
Boot reason. It can be any of the following values or combinations:
|
Items |
Description |
---|---|
Introduction |
Get boot reason |
Parameter |
None |
Return |
Boot reason. It can be any of the following values or combinations:
|