Cache

IC: RTL8721Dx RTL8720E RTL8726E RTL8730E

Introduction

The Cache of Soc supports Enable/Disable, Flush and Clean operation, as the following table lists.

Operation	Description	I-Cache	D-Cache
Enable/Disable	Enable or Disable Cache function	√	√
Flush (Invalidate)	Flush Cache D-Cache can be flushed by address Can be used after DMA Rx, and CPU reads DMA data from DMA buffer for D-Cache	√	√
Clean	Clean D-Cache D-Cache will be write back to memory D-Cache can be cleaned by address Can be used before DMA Tx, after CPU writes data to DMA buffer for D-Cache	x	√

Cache Boot Status

In the ROM code, the default states of Cache are:

RTL8721DxRTL8720ERTL8726ERTL8730E

• KM4 Cache: enabled by default

• KM0 Cache: disabled by default

Cache APIs

ICache_Enable

Items	Description
Introduction	Enable I-Cache
Parameters	None
Return	None

ICache_Disable

Items	Description
Introduction	Disable I-Cache
Parameters	None
Return	None

ICache_Invalidate

Items	Description
Introduction	Invalidate I-Cache
Parameters	None
Return	None

DCache_IsEnabled

Items	Description
Introduction	Check D-Cache enabled or not
Parameters	None
Return	D-Cache enable status: 1: Enable 0: Disable

DCache_Enable

Items	Description
Introduction	Enable D-Cache
Parameters	None
Return	None

DCache_Disable

Items	Description
Introduction	Disable D-Cache
Parameters	None
Return	None

DCache_Invalidate

Items	Description
Introduction	Invalidate D-Cache by address
Parameters	Address: Invalidated address (aligned to 32-byte boundary) Bytes: Size of memory block (in number of bytes)
Return	None

DCache_Clean

Items	Description
Introduction	Clean D-Cache by address
Parameters	Address: Clean address (aligned to 32-byte boundary) Bytes: size of memory block (in number of bytes) Note Address set 0xFFFFFFFF is used to clean all D-Cache.
Return	None

DCache_CleanInvalidate

Items	Description
Introduction	Clean and invalidate D-Cache by address
Parameters	Address: Clean and invalidated address (aligned to 32-byte boundary) Bytes: size of memory block (in number of bytes) Note Address set 0xFFFFFFFF is used to clean and flush all D-Cache.
Return	None

How to Define a Non-cacheable Data Buffer

RTL8721DxRTL8720ERTL8726ERTL8730E

Add SRAM_NOCACHE_DATA_SECTION before the buffer definition to define a data buffer with non-cacheable attribute.

SRAM_NOCACHE_DATA_SECTION u8 noncache_buffer[DATA_BUFFER_SIZE];

Note

TBD

Cache Consistency When Using DMA

When DMA is used to migrate data from/to memory buffers, the start address and end address of the buffer must be aligned with the cache line to avoid inconsistencies between cache data and memory data.

For example, if the start address of a buffer is in the middle of a cache line and the first half is occupied by other programs, invalidating or cleaning the current cache line by those programs will affect the entire cache line, resulting in inconsistent cache and memory data of the current buffer.

Note

The DMA operation address requires exclusive ownership of a full cache line. Define the buffer using malloc() or ALIGNMTO(CACHE_LINE_SIZE) u8 op_buffer[CACHE_LINE_ALIGMENT(op_buffer_size)].

DMA Tx Flow

1. CPU allocates Tx buffer

2. CPU writes Tx buffer

3. Realtek recommendation: call DCache_Clean()

4. DMA Tx configuration

5. DMA Tx interrupt handling

DMA Rx Flow

1. CPU allocates Rx buffer

2. DCache_Clean (if the Rx buffer is in a clean state, this step can be skipped)

   Caution

   • For Cortex-A32, if the Rx buffer is in a dirty state in the cache, executing DCache_Invalidate will perform both a clean and invalidate operation. The clean operation may lead to unexpected write behavior to memory.

   • If the Rx buffer is in a dirty state in the cache, the CPU may write the Rx buffer back to memory from the cache when the CPU’s D-Cache becomes full, which could overwrite the content that DMA has already written.

3. DMA Rx configuration

4. DMA Rx interrupt handling

5. DCache_Invalidate (this step is mandatory)

Caution

• For CPUs with automatic data prefetching and monitoring capabilities, such as Cortex-A32/DSP, e.g., Cortex-A32 reads the contents of adjacent addresses of the Rx buffer, Cortex-A32 starts line fills in the background to bring the old values of the Rx buffer back into the cache.

• Prevents the CPU from reading old values into the cache during DMA processing.

6. CPU reads Rx buffer (the value returned by DMA Rx)

   Caution

   For Cortex-A32/DSP, DCache_Clean/DCache_CleanInvalidate operations write entire cache lines to memory. When two CPUs (with different cache line sizes) communicate using a shared memory region, this shared memory must be aligned with the larger of the two cache line sizes. e.g., if the shared memory is only 32 bytes, CPU0 with a 32-byte cache line will only write 32 bytes each time it cleans, while CPU1 with a 64-byte cache line will write 64 bytes each time it cleans, potentially overwriting other data of CPU0.