IC: RTL8721Dx RTL8720E RTL8726E RTL8730E

Overview

What is PSRAM?

PSRAM (Pseudo Static Random Access Memory) is a type of memory that combines the ease-of-use of SRAM with the high-density characteristics of DRAM. It achieves an SRAM-like interface through dynamic refresh mechanisms.

PSRAM Features

• Periodic Auto-Refresh: Automatically maintains data integrity transparently to software, eliminating the need for explicit refresh management.

• Temperature-Adaptive Refresh: Integrated temperature sensor shortens refresh intervals in high-temperature environments (>85°C) and extends intervals at lower temperatures, optimizing power efficiency.

• High-Speed Access: Supports fast data processing with low latency.

• Simplified Interface: Easy-to-integrate SRAM-compatible interface.

• Medium Density: Provides higher storage capacity than SRAM at a lower cost.

PSRAM Applications

• Embedded Systems: IoT devices, audio equipment, Wi-Fi modules.

• Display Buffering: LCD/OLED screen drivers for graphics rendering.

• Low-Power Scenarios: Battery-powered devices requiring energy-efficient memory solutions.

• Real-Time Data Processing: Sensor data caching and communication protocol stacks.

PSRAM Architecture

Physical Structure

• Memory Cell: Based on DRAM capacitive structure with integrated internal refresh controller.

• Parallel Interface: Data lines (DQ0~DQn), control signals (CS, CK/CK#, DQS, RESET).

• Dual-Edge Triggering: Supports DDR (Double Data Rate) transmission mode.

• Operating Voltage: 1.7~2.0V (Core voltage: 1.8V).

Control Architecture

• PHY Layer: Handles timing calibration, programmable drive strength, and signal integrity enhancement.

• SPIC Controller: Manages timing control, protocol conversion, arbitration, and refresh operations.

• Master: CPU, DMA, CRYPTO, WIFI, and other peripherals with direct access capability.

psram control architecture

Functional Features

• Random Access: Supports read/write operations at arbitrary addresses.

• Burst Access: Enables consecutive data transfers for improved throughput efficiency.

• Standby Mode: Powers down partial circuits while retaining stored data.

• Deep Sleep Mode: Disables all functional circuits and halts refresh operations, resulting in data loss in memory cells.

PSRAM Usage Guide

Automatic PSRAM Initialization

• Post-Boot Initialization:

  The SDK automatically detects whether the chip integrates PSRAM (Pseudo Static RAM) during device boot, then performs model identification and initialization.

  Initialization Log Example:

  15:12:01.724  [PSRAM-I] PSRAM Ctrl CLK: 400000000 Hz
  15:12:01.724  [BOOT-I] Init WB PSRAM
  

• DQS Delay Calibration:

After initialization, the SDK automatically performs PSRAM DQS delay calibration by dynamically adjusting the phase alignment between DQS and DQ signals, optimizing signal sampling windows.

Calibration Log Examples (Success: WindowSize ≥ 9):

15:12:01.724  [PSRAM-I] CalNmin = 2 CalNmax = 17 WindowSize = 16 phase: 0

Memory Layout (LD) Planning

• Configure PSRAM link policies via menuconfig:

PSRAM Usage Notes

Using Winbond PSRAM in High-Temperature Environments

Distributed Row Refresh

• Dynamically scatters refresh operations through hardware-automated scheduling, transparent to software. The standard 196ms refresh cycle is divided into multiple evenly spaced refresh commands inserted between normal access intervals, preventing bandwidth occupation from concentrated refresh operations.

TCEM (Chip Select Low-Level Maximum Time)

• The maximum interval for distributed refresh is determined by TCEM. TCEM configuration must be manually adjusted based on actual operating temperatures. The SDK defaults to room temperature (T ≤ 85°C) parameters. For high-temperature scenarios (T > 85°C), users must modify the code as follows to ensure data reliability:

Configuration Rules:

PSRAM Self-Refresh Rules

Temperature Range	Refresh Strategy	Max Refresh Interval
T ≤ 85°C	Standard Refresh Mode	4μs
85°C < T ≤ 125°C	Enhanced Refresh Mode	1μs

Modification Steps

• Locate Code File:

  Open ameba_psram.c in the SDK and find the PSRAM_CTRL_Init() function.

• Modify Code:

   // High-temperature mode configuration (T > 85°C)
   psram_ctrl->TPR0 = (CS_TCEM(Psram_Tcem_T85 * 1000 / PsramInfo.PSRAMC_Clk_Unit / 32) |
                     (TPR0_OTHER_FIELDS));

Row Hammer Effect Mitigation

Physical Mechanism and Risks

• Cause: Frequent access to target rows (Aggressor Rows) causes abnormal charge leakage in adjacent row (Victim Row) capacitors due to the charge leakage characteristics of DRAM-based memory cells.

• Consequences: Single-Bit Flip (SEU) or Multi-Bit Flip (MBU).

Protection Strategies

• Distributed Row Refresh

• Cache Access Dilution: - Prefetch Buffer: Merges random accesses into burst transfers, reducing physical row activations. - Write Combining: Aggregates scattered write operations to minimize row switching.

Reliability Validation Data

PSRAM Stress Test Data

Test Parameter	Metric
Environmental Condition	125°C, 1.05V Overvoltage
Attack Intensity	8.33M Row Activations/sec
Test Duration	24 Hours Continuous Run
Data Integrity	0 Bit Flips Detected

• With Cache enabled, physical row activation frequency remains far below test values (8.33M ops/sec).

• Combined with hardware-level distributed refresh, Row Hammer-induced errors are fully eliminated.

• Normal usage patterns do not trigger high-frequency row activations.

Note

Conclusion: With Cache and hardware protection mechanisms working synergistically, Row Hammer risks are reduced to theoretically negligible levels, requiring no additional protection logic design.

PSRAM TP

Measured Data:

PSRAM supports both direct access and DMA access modes. The throughput performance metrics are shown in the following tables:

RTL8721DxRTL8720ERTL8726ERTL8730E

Throughput of PSRAM (200MHz)

Access mode	Writing 32 bytes		Reading 32 bytes
	Theory	Test on the KM4	Theory	Test on the KM4
Direct access (write back)	1523.81Mbps	(32*8)/(199.68ns)=1282.05Mbps	1454.55Mbps	(32*8)/(212.16ns)=1204.14Mbps
DMA access		1088.64Mbps		1092.27Mbps

Performance Test Notes:

• Throughput Theoretical Calculation Basis:

  • Test data includes variable initial latency. The specific latency cycles (1T or 2T) are determined by the RWDS signal.

  • The packet header overlaps with latency by 1T.

  • As DDR PSRAM is used, transmitting 32 bytes requires 16 clock cycles (16T).

• Direct Access Characteristics:

  • By default, the cache attribute is enabled for PSRAM. Performance testing must comprehensively consider cache impacts.

  • 4-byte Read Operation:

    • Cache Hit: CPU directly reads 4 bytes from the cache.

    • Cache Miss: Requires reading a full cache line (cacheline size) from PSRAM to the cache.

  • 4-byte Write Operation:

    • Cache Hit: Updates cache data. The full cache line is written back to PSRAM during cache flush.

    • Cache Miss: Following the write-allocate policy, the CPU first reads a full cache line from PSRAM to the cache before updating the cache data.

  • Read/Write throughput data in the table is measured under cache miss/flush scenarios (i.e., forced PSRAM access).

  • Throughput of write-allocate mode equals that of cache miss read scenarios.

  • Theoretical values exclude instruction execution time overhead.

Theoretical Calculation Methodology:

Calculation Formulas：

Total Time Consumption = [CMD + ADDR + (LC-1)] × T_PSRAM + Data Transmission Period + Hardware Hold Time

Theoretical Throughput = (Data Bit Width) / Total Time Consumption

Parameter Descriptions：

Throughput Calculation Parameters

Parameter	Calculation Method	Parameter Description	Value/Unit
TPSRAM	1 / Clock Frequency	PSRAM Clock Cycle	Example: 150MHz→6.667ns
CMD + ADDR	Fixed 3 Cycles	Command Phase Overhead	3 cycles
LC	Latency Cycle	Determined by PSRAM Model and Clock	Example: 6 cycles
Data Bit Width	32 bytes = 256 bits (32×8)	Single Transmission Data Volume	256 bits
Data Transfer Cycle	32/2 × TPSRAM	32-bit Data Requires 16 Clock Cycles for Transmission	16×TPSRAM
Hardware Hold Time	Write Operation: 1 Cycle	Bus Release Buffer Time	1 or 2 cycles
	Read Operation: 2 Cycles